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<title>ANDN — Logical AND NOT </title></head>
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<h1>ANDN — Logical AND NOT</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op/En</th>
<th>64/32 -bit Mode</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
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<td>VEX.NDS.LZ.0F38.W0 F2 /r ANDN r32a, r32b, r/m32</td>
<td>RVM</td>
<td>V/V</td>
<td>BMI1</td>
<td>Bitwise AND of inverted r32b with r/m32, store result in r32a.</td></tr>
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<td>VEX.NDS.LZ. 0F38.W1 F2 /r ANDN r64a, r64b, r/m64</td>
<td>RVM</td>
<td>V/NE</td>
<td>BMI1</td>
<td>Bitwise AND of inverted r64b with r/m64, store result in r64a.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
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<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
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<td>RVM</td>
<td>ModRM:reg (w)</td>
<td>VEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr></table>
<h2>Description</h2>
<p>Performs a bitwise logical AND of inverted second operand (the first source operand) with the third operand (the second source operand). The result is stored in the first operand (destination operand).</p>
<p>This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.</p>
<h2>Operation</h2>
<pre>DEST ← (NOT SRC1) bitwiseAND SRC2;
SF ← DEST[OperandSize -1];
ZF ← (DEST = 0);</pre>
<h2>Flags Affected</h2>
<p>SF and ZF are updated based on result. OF and CF flags are cleared. AF and PF flags are undefined.</p>
<h2>Intel C/C++ Compiler Intrinsic Equivalent</h2>
<p>Auto-generated from high-level language.</p>
<h2>SIMD Floating-Point Exceptions</h2>
<p>None</p>
<h2>Other Exceptions</h2>
<p>See Section 2.5.1, “Exception Conditions for VEX-Encoded GPR Instructions”, Table 2-29; additionally</p>
<table class="exception-table">
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<td>#UD</td>
<td>If VEX.W = 1.</td></tr></table></body></html>